Computer systems that employ a processor, such as a CPU, often utilize a memory controller. The memory controller controls access by the processor and other agents to a memory, such as main memory. The main memory is typically implemented using arrays of Dynamic Random Access Memory (DRAM). When the memory remains inactive for a given period of time, it is advantageous to close its pages so that future requests to the memory will be performed with “page empty” timing. Performance gain is typically realized when future requests result-in more “page misses” than “page hits.” Conversion to page empties thus increases memory efficiency and reduces latency. Additionally, when page closing is aggressive, subsequent page hits will be converted to page empty accesses, thus increasing latency.
A memory idle timer value determines the number of host bus clock cycles that the memory controller will remain in the idle state before open pages are closed. Typically, different benchmarks perform better with different memory idle timer settings. In particular, some benchmarks perform best when an aggressive memory idle timer setting of zero (0) clock cycle is used, while others perform best with memory idle timer settings of eight (8), sixteen (16) or infinite clock cycles. In some cases, the performance swing between the best and worst selection of memory idler timer values is significant.
After each memory access, the number of idle memory clocks is counted and if there are no same page requests, the page is closed. For example, after a memory read or write request, the system waits for a fixed amount of memory clocks and determines whether there is a request from that page. If there is none, the page is closed.
Conventionally, the memory idle timer timeout value is set by BIOS at boot and never changed. This static memory idle timer value will be a compromise of results for various benchmarks. Finding out the compromise value for the memory idle timer is typically a time consuming and inefficient process.